\doxysection{PSSI\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_p_s_s_i___type_def}{}\label{struct_p_s_s_i___type_def}\index{PSSI\_TypeDef@{PSSI\_TypeDef}}


PSSI.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_ae0c882dfbd354da63f59e9e42bfe3877}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a9e0917888f230c3b231be7a55ab40f13}{SR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a847518ccffdad17a0410db44fd0ec7bd}{RIS}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a481282a747e2fd419c485360e1e4f605}{IER}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a79db5fbabc54e24880ac3a1fced18b21}{MIS}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a84c989c4c55349705152767fc88caa19}{ICR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a1a680c932b421a0757c83081a8ed032b}{RESERVED1}} \mbox{[}4\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a06dcca94887edb4a692f1bc663eb130e}{DR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_ad5c5e0a27a4e0cb6340bee4fb3097d43}{RESERVED2}} \mbox{[}241\mbox{]}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_a4bc8fe3c181d5c9da16955fb221d3813}{HWCFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_ada3166b14e2ae8d86a08671163c011d6}{VERR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_ac6efda3c9517cd865b389e5c385dae37}{IPIDR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_p_s_s_i___type_def_abdcc7e0e2d580f161ccdd7a0f012271d}{SIDR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
PSSI. 

\label{doc-variable-members}
\Hypertarget{struct_p_s_s_i___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_p_s_s_i___type_def_ae0c882dfbd354da63f59e9e42bfe3877}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!CR@{CR}}
\index{CR@{CR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_ae0c882dfbd354da63f59e9e42bfe3877} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+CR}

PSSI control register 1, Address offset\+: 0x000 \Hypertarget{struct_p_s_s_i___type_def_a06dcca94887edb4a692f1bc663eb130e}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!DR@{DR}}
\index{DR@{DR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{DR}{DR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a06dcca94887edb4a692f1bc663eb130e} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+DR}

PSSI data register, Address offset\+: 0x028 \Hypertarget{struct_p_s_s_i___type_def_a4bc8fe3c181d5c9da16955fb221d3813}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!HWCFGR@{HWCFGR}}
\index{HWCFGR@{HWCFGR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{HWCFGR}{HWCFGR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a4bc8fe3c181d5c9da16955fb221d3813} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+HWCFGR}

PSSI IP HW configuration register, Address offset\+: 0x3\+F0 \Hypertarget{struct_p_s_s_i___type_def_a84c989c4c55349705152767fc88caa19}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a84c989c4c55349705152767fc88caa19} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+ICR}

PSSI interrupt clear register, Address offset\+: 0x014 \Hypertarget{struct_p_s_s_i___type_def_a481282a747e2fd419c485360e1e4f605}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!IER@{IER}}
\index{IER@{IER}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IER}{IER}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a481282a747e2fd419c485360e1e4f605} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+IER}

PSSI interrupt enable register, Address offset\+: 0x00C \Hypertarget{struct_p_s_s_i___type_def_ac6efda3c9517cd865b389e5c385dae37}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!IPIDR@{IPIDR}}
\index{IPIDR@{IPIDR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{IPIDR}{IPIDR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_ac6efda3c9517cd865b389e5c385dae37} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+IPIDR}

PSSI IP ID register, Address offset\+: 0x3\+F8 \Hypertarget{struct_p_s_s_i___type_def_a79db5fbabc54e24880ac3a1fced18b21}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!MIS@{MIS}}
\index{MIS@{MIS}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{MIS}{MIS}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a79db5fbabc54e24880ac3a1fced18b21} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+MIS}

PSSI masked interrupt status register, Address offset\+: 0x010 \Hypertarget{struct_p_s_s_i___type_def_a1a680c932b421a0757c83081a8ed032b}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!RESERVED1@{RESERVED1}}
\index{RESERVED1@{RESERVED1}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED1}{RESERVED1}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a1a680c932b421a0757c83081a8ed032b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+RESERVED1\mbox{[}4\mbox{]}}

Reserved, 0x018 -\/ 0x024 \Hypertarget{struct_p_s_s_i___type_def_ad5c5e0a27a4e0cb6340bee4fb3097d43}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!RESERVED2@{RESERVED2}}
\index{RESERVED2@{RESERVED2}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RESERVED2}{RESERVED2}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_ad5c5e0a27a4e0cb6340bee4fb3097d43} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+RESERVED2\mbox{[}241\mbox{]}}

Reserved, 0x02C -\/ 0x3\+EC \Hypertarget{struct_p_s_s_i___type_def_a847518ccffdad17a0410db44fd0ec7bd}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!RIS@{RIS}}
\index{RIS@{RIS}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{RIS}{RIS}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a847518ccffdad17a0410db44fd0ec7bd} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+RIS}

PSSI raw interrupt status register, Address offset\+: 0x008 \Hypertarget{struct_p_s_s_i___type_def_abdcc7e0e2d580f161ccdd7a0f012271d}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!SIDR@{SIDR}}
\index{SIDR@{SIDR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SIDR}{SIDR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_abdcc7e0e2d580f161ccdd7a0f012271d} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+SIDR}

PSSI SIZE ID register, Address offset\+: 0x3\+FC \Hypertarget{struct_p_s_s_i___type_def_a9e0917888f230c3b231be7a55ab40f13}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!SR@{SR}}
\index{SR@{SR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{SR}{SR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_a9e0917888f230c3b231be7a55ab40f13} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+SR}

PSSI status register, Address offset\+: 0x004 \Hypertarget{struct_p_s_s_i___type_def_ada3166b14e2ae8d86a08671163c011d6}\index{PSSI\_TypeDef@{PSSI\_TypeDef}!VERR@{VERR}}
\index{VERR@{VERR}!PSSI\_TypeDef@{PSSI\_TypeDef}}
\doxysubsubsection{\texorpdfstring{VERR}{VERR}}
{\footnotesize\ttfamily \label{struct_p_s_s_i___type_def_ada3166b14e2ae8d86a08671163c011d6} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t PSSI\+\_\+\+Type\+Def\+::\+VERR}

PSSI IP version register, Address offset\+: 0x3\+F4 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
